1. Field of the Invention
The present invention relates to a method and an apparatus for dynamically configuring the redundant area in a non-volatile memory and, more particularly, to a method and an apparatus for configuring data areas and redundant areas in a flash memory and reducing the buffer size of the storage device for accessing data.
2. The Related Arts
Flash memory is widely used in versatile digital equipment, such as digital cameras, TV game boxes, and flash drives. As the fabrication technology improves, the capacity of flash memory also increases greatly. For example, FIG. 1 shows the 1G-bit flash memory chip 1 manufactured by Samsung. The flash memory has the capacity of 128M bytes, divided into 1024 blocks 11, with each block having 64 pages 12. In each page 12, there are 2K+64 bytes, where 2K bytes are the data area 121, and the 64 bytes are the redundant area 122, located at the end of the data area 121 for storing system information of the flash memory 1. The system information comprises the flag or the status parameter to indicate whether the data area 121 of the memory block 11 is damaged. The flag or the state parameter is referenced while accessing the flash memory 1.
However, the structure of data area 121 and redundant area 122 in the flash memory 1 cannot be accessed by the conventional flash memory controller because the buffer size of the conventional flash memory controller is too small. In general, the IC designers have to redesign the controller to cooperate with the new flash memory. For example, the conventional controller has a pair of 528-byte ping-pong buffers (total of 1056 bytes) for accessing a memory structure with a 512-byte data area and a 16-byte redundant area. The buffers are unable to accommodate the data area 121 and the redundant area 122 as shown in FIG. 1 (total of 2112 bytes). Therefore, it is necessary to develop a new flash memory controller to access the new flash memory structures, such as the flash memory 1. Thus, the re-develpoment of the FIFO control circuit in the controller and the associated firmware to access the new 2K+64-byte buffer is necessary for the prior art. This does not only take time and high cost but also delay the product's mass production schedule